Signal Processing with MATLAB and Simulink: Model to Code Made Simple
Τετάρτη 05/04/2017 - 17:00

Το σεμινάριο απευθύνεται σε μηχανικούς – στελέχη εταιριών και επιχειρήσεων με δραστηριότητα στη σχεδίαση και υλοποίηση αλγορίθμων, που θέλουν να ενημερωθούν και να δουν μέσα από αναλυτικά παραδείγματα τις δυνατότητες του MATLAB και του Simulink.

Θα χρησιμοποιηθούν πλήρως λειτουργικά μοντέλα υλοποιημένα σε hardware, όπως Xilinx ZC-702, ZYBO ARM/FPGA SoC board και Xilinx Zedboard, προκειμένου να παρουσιαστούν οι δυνατότητες του λογισμικού σε διαδικασίες όπως:

  • Επεξεργασία σήματος και εικόνας
  • Τηλεπικοινωνίες
  • Embedded Systems / FPGA Design
  • Ανάπτυξη λογισμικού
  • Μοντελοποίηση Συστημάτων
  • Design Verification and Validation


Ν. Νικοδήμου 18-20, ΑΘΗΝΑ - Αίθουσα BALLROOM 1  ( ΧΑΡΤΗΣ )

Το σεμινάριο είναι ΔΩΡΕΑΝ και θα γίνει στα Αγγλικά. Για να εξασφαλίσετε τη συμμετοχή σας, παρακαλούμε συμπληρώστε τα στοιχεία σας στην φόρμα εγγραφής.

Θα τηρηθεί σειρά προτεραιότητας. Η συμμετοχή σας θα επιβεβαιωθεί με απαντητικό email.


Sébastien Dupertuis

Senior Application Engineer, MathWorks

Sébastien Dupertuis is a senior application engineer at MathWorks Switzerland. He works in the area of design automation with a focus on signal processing and code generation technologies targeting heterogeneous embedded systems. Sébastien held software engineering-related positions for over 5 years at Institut d’Automatisation Industrielle as well as Swissvoice in Switzerland. At Swissvoice, he was in charge of developing the audio part and the automatic testing framework for DECT phones. Sébastien graduated as a telecommunication engineer from La Haute Ecole d'Ingénierie et de Gestion du Canton de Vaud and as a physicist from the University of Geneva. 

Seminar Overview

MathWorks signal processing and communication products provide extensive tools and algorithm libraries that let you analyze, design, and simulate DSP and communications systems in a fraction of the time it takes with traditional programming languages such as C and C++.

Within a single, integrated algorithm and system development environment, you can:

  • Acquire measured data and analyze signals
  • Develop algorithms for signal processing, communications, audio, and video applications
  • Simulate the effect of real-world conditions and system-level interactions on algorithm behavior
  • Generate C or HDL code for execution on embedded DSPs, ASICs, and FPGAs

During this seminar you will learn how to use MATLAB and Simulink in various tasks common to engineers, researchers and developers all over the world working with DSP and communication system design.

We will focus on the use of MATLAB and Simulink as an integrated environment that can be used during the entire development process of a product or application – from idea to implementation.

Examples shown in this seminar will range from signal processing tasks such as acquiring data, filter design, acoustic noise cancellation etc., to complete system design examples including automatic generation and verification of C and HDL code targeting DSPs, ASICs and FPGAs.

Reasons to attend this seminar:

  • Expand your awareness of what is possible to do with MATLAB and Simulink
  • Become more efficient in how you use MATLAB and Simulink
  • Learn how MATLAB/Simulink can be used  as powerful product a development tools
  • Use this opportunity to interact with MathWorks representatives
  • Meet other users of MATLAB and Simulink
  • See what’s new in R2017a



Who Should Attend?

  • Researchers and Students
  • Signal Processing Engineers
  • Communications System Engineers
  • Software/Hardware Engineers

Seminar Highlights

  • Model-Based Design
  • System Toolboxes
  • Fixed-Point Design
  • C  and HDL Code Generation
  • Verification of Systems using Co-Simulation and FPGA-in-the-Loop

This seminar is appropriate for both new and experienced users.





17:00 – 17:30

Προσέλευση – Καφές

17:30 – 17:35   

Welcome & Introduction

17:35 – 18:45        

Signal Processing with MATLAB and Simulink


  • From Filter Design in Time and Frequency Domains to Deployment onto Hardware
  • Real Analog Filter Design using Physical Components

18:45 – 19:05

Coffee Break & Networking

19:05 – 20:20        

Model to Code Made Simple


  • Model-Based Design Workflow
  • Requirements Traceability Between Model, Specification and Code
  • Multidomain Modelling for C, C++, HDL and PLC Code Generation
  • In-the-Loop Verification Methodologies using Xilinx Zynq ZedBoard, Xilinx ZC-702 and ZYBO ARM/FPGA SoC board

20:20 – 20:30       

What's New in 2017a

20:30 – ...

Summary, Next Steps, Q&A

Για να εξασφαλίσετε τη συμμετοχή σας, παρακαλούμε συμπληρώστε τα στοιχεία σας στην φόρμα εγγραφής. Θα τηρηθεί σειρά προτεραιότητας.